CONIX Publication

Partial Reconfiguration for Design Optimization

Authors: James Hoe


FPGA designers have traditionally shared a similar design methodology with ASIC designers. Most notably, at design time, FPGA designers commit to a fixed allocation of logic resources to modules in a design. At runtime, some of the occupied resources could be left under-utilized due to hard-to-avoid sources of inefficiencies (e.g., operation dependencies, unbalanced pipelines). This work is relevant to applications within CONIX that (1) can benefit from FPGA acceleration and (2) are resource or device cost constrained. If mapped traditionally on the FPGA (i.e. without PR), under-utilization may result in (1) the design not running at the desired performance given an area budget, or (2) the design running at the desired performance but being too big to fit in the given area. With partial reconfiguration (PR), FPGA resources can be re-allocated over time. Therefore, using PR, a designer can attempt to reduce slack, or under-utilization, with better time-space scheduling. In this work, we first introduce the concept of area-time volume to explain why PR-style designs can improve upon ASIC-style designs. We identify slack as an opportunity that can be exploited by PR-style designs. We then present a first-order analytical model to help a designer decide if a PR-style design can be beneficial. When it is the case, the model points to the most suitable PR execution strategy and provides an estimate of the improvement. The model is validated in three case studies.

Release Date: 10/13/2020
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